IBM Unveils Groundbreaking Sub-1 Nanometer Chip Technology

On June 25, 2026, International Business Machines Corporation (IBM) made headlines with the announcement of the world's first sub-1 nanometer (nm) chip technology. This breakthrough showcases a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node, signifying a monumental achievement for the semiconductor industry, which is grappling with the physical limitations of traditional chip scaling. Semiconductors are integral to modern technology, powering everything from computers and appliances to communication devices and critical infrastructure.

IBM's new sub-1 nm chip boasts nearly 100 billion transistors packed into a chip the size of a fingernail. This is nearly double the density compared to IBM's previous 2 nm chip launched in 2021. The newly developed chip is projected to deliver a staggering increase in capability—up to 50% more performance and 70% greater energy efficiency than its 2 nm counterparts. This leap in technology is set to supercharge computing applications ranging from generative AI and cloud infrastructure to the next generation of electronic devices.

Jay Gambetta, Director of IBM Research and an IBM Fellow, stated, "IBM's latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we're not just making smaller transistors; we're reinventing how chips are built to deliver dramatically more power and energy efficiency." This innovation underscores IBM's commitment to leading next-generation technologies and sets the stage for the future of computing.

Central to this innovation is the novel "nanostack" architecture, the first known three-dimensional, nanosheet-based design in the industry. This architecture represents a significant advancement over existing nanosheet technology, originally developed by IBM. The nanostack design vertically stacks and staggers transistors, utilizing 3D sequential integration to increase transistor density on the chip. Furthermore, it allows for the use of various material combinations within each stacked layer, optimizing the performance and power efficiency of each transistor independently.

Experimental validation of the nanostack architecture was demonstrated through ultra-thin dielectric bonding in complementary metal-oxide-semiconductor (CMOS) integration and functional CMOS inverter operation, confirming the practical viability of the technology. Additionally, research presented at VLSI 2026 illustrated that the nanostack architecture facilitates a 40% scaling in SRAM, enabling chip designers to produce more efficient chips while meeting the high-bandwidth demands of advanced AI workloads.

This breakthrough allows logic technology to extend below the 1 nm node for the first time, ushering in an era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes historically referred to a generation of manufacturing technology rather than an exact physical dimension, IBM's 0.7 nm technology demonstrates that continued scaling is feasible. The company's semiconductor roadmap indicates a potential for at least a decade of further scaling advancements.

IBM's latest achievement serves as a testament to its longstanding leadership in semiconductor research and development. The company has been at the forefront of semiconductor innovation for decades, producing the chips that drive computing systems from the early days of semiconductors in the 1960s to the introduction of the world's first 2 nm node chip.

This groundbreaking endeavor is conducted at IBM's leading semiconductor research facility in Albany, New York, which is set to house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, critical for future logic scaling. Collaborations with industry partners, including Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd., have already yielded promising results in the development of new High NA EUV processes and tools.

In addition, IBM recently announced plans to establish Anderon, the world's first pure-play quantum foundry. This standalone company aims to leverage IBM's expertise in quantum computing and semiconductor technology to bolster the United States' position in the global quantum wafer manufacturing landscape.

With the anticipated earliest adoption of nanostack technology at the sub-1 nm node, IBM envisions a path to production within the next five years. This innovation not only enhances IBM's semiconductor technology portfolio but also sets the stage for the next era of computing, emphasizing the company's commitment to advancing technology in an increasingly digital world.