Synopsys Partners with TSMC to Propel AI and Multi-Die Innovation

On September 24, 2025, Synopsys, Inc. (Nasdaq: SNPS) announced an exciting extension of its collaboration with Taiwan Semiconductor Manufacturing Company (TSMC). This partnership aims to deliver advanced multi-die solutions, utilizing state-of-the-art Electronic Design Automation (EDA) and Intellectual Property (IP) products that support TSMC’s cutting-edge processes and packaging technologies. This collaboration is poised to drive significant advancements in AI chip design and multi-die architectures, marking a pivotal moment in semiconductor innovation.

The strategic alliance has yielded notable developments, including the introduction of the 3DIC Compiler exploration-to-signoff platform and a robust suite of IP solutions specifically tuned for 3D packaging. With these innovations, Synopsys and TSMC have achieved multiple customer tape-outs, showcasing their effectiveness in real-world applications.

Michael Buehler-Garcia, Senior Vice President at Synopsys, commented, "Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape-outs on the industry's most advanced packaging and process technologies." He emphasized how Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs that offer enhanced performance while reducing power consumption and accelerating time to market.

A key highlight of the partnership is the certification of Synopsys’ digital and analog flows, which are optimized for TSMC’s N2P and A16™ processes utilizing TSMC NanoFlex™ architecture. This certification ensures that Synopsys’ tools are well-equipped to meet the demands of high-performance, energy-efficient chip designs. The certified capabilities for TSMC A16™ Super Power Rail (SPR) process notably improve power distribution and system performance, underscoring the collaboration's commitment to innovation.

The 3DIC Compiler platform has been further enhanced to support TSMC's SoIC® (System on Integrated Chip) technology, which includes advanced 3D stacking and CoWoS® (Chip-on-Wafer-on-Substrate) technologies. These advancements aim to improve productivity and reduce turnaround times for customers by automating critical tasks such as UCIe and HBM routing, TSV (Through-Silicon Via) planning, and multi-die signoff verification.

Moreover, Synopsys and TSMC are working together on silicon photonics, resulting in an AI-optimized photonic IC flow for TSMC-COUPE™ technology. This technology addresses multi-wavelength and thermal requirements in complex multi-die and AI designs, paving the way for enhanced system performance.

Synopsys' extensive portfolio of IP solutions is another cornerstone of this collaboration, designed to accelerate semiconductor innovation across TSMC's upcoming N2P/N2X processes. The portfolio includes high-performance standards such as HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, alongside a robust roadmap for automotive, IoT, and High-Performance Computing (HPC) applications.

The company provides a comprehensive suite of high-performance PHYs, embedded memories, high-density logic libraries, programmable I/O, and NVM IP, all aimed at meeting the demanding specifications of next-generation designs across various markets.

As Synopsys continues to strengthen its collaboration with TSMC, both companies are set to host discussions at TSMC's OIP Forums, where mutual customers will share their experiences with the new offerings. Moreover, Synopsys will showcase several demonstrations at Booth #204, highlighting the innovative capabilities made possible through this partnership.

In summary, Synopsys’ collaboration with TSMC represents a significant leap forward in the semiconductor industry, particularly in the realm of AI and multi-die innovations. With a shared vision for high-quality, energy-efficient designs, this partnership is well-positioned to shape the future of chip design and manufacturing.